For the past 30 years, the size of a metal-oxide-semiconductor field-effect-transistor (MOSFET) in very-large-scale integrated circuits (VLSI) continued to scale down for higher integration and higher performance. As the gate length of MOSFETs has reached down to sub-50 nm, unprecedented technical issues have become prominent to proceed scaling of the MOSFETs.

Silicon single-electron transistor/single-hole transistor (SET/SHT) is one of the most promising devices for VLSI in silicon nanotechnology; the technology that seeks new function in nano structures. Although its operation principle is different from conventional MOSFETs, its fabrication process is very similar to them. Hence, it is expected that SETs/SHTs can be easily combined with CMOS VLSI and realize high functional, ultra-low power, and ultra-high density circuits. Owing to the intensive researches on SETs/SHTs, process techniques for SETs/SHTs to operate at room temperature have been establishes. In such room-temperature operating SETs/SHTs, strong quantum effect has become pronounced and started to affect the transport characteristics. However, basic analysis and enhancement of the device performance are still required for room-temperature-operating SETs/SHTs to be used in actual VLSI circuits.

In this dissertation, characteristics of the room-temperature-operating SETs/SHTs are analyzed and their advantages are fully enhanced aiming at the actual VLSI circuit applications. The feasibilities of the proposed methods are evaluated by simulations and measurements.

In the first half of the Chapter 2, characteristics of the SETs/SHTs is introduced starting from the fundamentals of the SET/SHT physics. Coulomb blockade oscillation and other important current characteristics in SET/SHT are derived from the classical physics. For the systems that quantum mechanical effects matters, quantum level spacings should be take into account. In silicon (semiconductor) SETs/SHTs, quantum effects play important roles in their transport characteristics. NDC is supposed to be the most promising quantum effects to be utilized in novel high function circuits. In the second half, some fabrication methods of the room-temperature operating SETs/SHTs are discussed. Ultra-narrow channel MOSFETs is introduced as the best method in terms of room-temperature operation. The mechanism of the formation of the tunnel barriers and quantum dots are explained. Channel potential fluctuation in undulated ultra-narrow channel by lithography, wet etching and thermal oxidation processes are the dominant origins.

In Chapter 3, a compact analytical SET/SHT model considering the discrete quantum energy levels is proposed and developed. The model is expressed in closed-form and there is no need of numerical calculation. It successfully reproduces NDC characteristics and non-periodic Coulomb oscillations due to the finite quantum level spacings. It also shows that the accuracy is comparable to the conventional full master equation method and fits well to the measured data. The model is incorporated into the HSPICE simulation, and basic NDC circuit applications are demonstrated. The proposed analytical model is promising to provide suitable environments for designing CMOS-combined room-temperature- operating highly-functional SET circuits.

In Chapter 4, the relationship between the FWHM of the NDC and voltage gain is focused for the first time and it is found by the experiments and calculations that high gain SETs/SHTs show small FWHM in NDC. Low drain-dot coupling in the high gain SETs/SHTs is considered to be the most important factor. This result indicates that characteristics of the NDC are able to design by the basic capacitance parameters of the SETs/SHTs. From the viewpoint of applications, high-gain SETs/SHTs have great advantage to NDC circuits as well as to the standard logic circuits.

In Chapter 5, FWHM of Coulomb blockade peak is modulated in a SHT at room temperature by varying substrate capacitance through changing the substrate condition from depletion to accumulation (inversion) in a thin BOX SOI substrate. The results are also quantitatively supported by the low temperature measurements in another fabricated SHT. The electrical control of the sharpness of the Coulomb blockade peak creates great opportunity for adding further functionality to the present SETs/SHTs, such as application to the novel analog pattern matching device. Also, the guide lines to increase the proposed effects for practical use are discussed.

本論文は,「Study on Applications of Room-Temperature Operating Silicon Single-Electron Transistors」(和訳:室温動作シリコン単電子トランジスタとその応用)と題し,英文で書かれている.本論文は,室温動作のシリコン単電子トランジスタの特異な特性を応用するための技術とその可能性を論じたもので,全6章より構成される.

第1章は「Introduction」(序論)であり,大規模集積回路を構成するMOS電界効果トランジスタの微細化の状況をまとめるとともに,新しい原理で新機能をもたらす単電子トランジスタの必要性とその課題を述べており,本論文の背景と目的を明確にしている.

第2章は,「Room-Temperature-Operating Silicon Single-Electron/Single-Hole Transistors and Their Characteristics」(室温で動作するシリコン単電子・単正孔トランジスタとその特性)と題し,室温動作単電子トランジスタの特性に現れるクーロンブロッケード振動と負性微分コンダクタンス特性の基礎をまとめている.また,室温動作の単電子・単正孔トランジスタを作製するためのプロセスと,直径数ナノメートルという微小量子ドットが形成される機構について述べている.

第3章は,「Compact Analytical Model for Room-Temperature-Operating Single-Electron/Single-Hole Transistors with Discrete Quantum Energy Levels」(離散量子準位を有する室温動作単電子・単正孔トランジスタのコンパクト解析モデル)と題し,室温動作単電子トランジスタを用いた回路をシミュレーションするためのデバイスモデルについて論じている.室温動作の単電子トランジスタでは量子ドットが極めて小さいため離散量子準位を考慮する必要がある.実験で観測される負性微分コンダクタンスおよび非周期的クーロンブロッケード振動を再現することに成功し,HSPICEにて簡単な回路シミュレーションを行う環境の構築に成功している.

第4章は,「Control of the Negative Differential Conductance Characteristics in Silicon Single-Hole Transistors」(シリコン単正孔トランジスタにおける負性微分コンダクタンス特性の制御)と題し,単正孔トランジスタのパラメータ変化させることにより負性微分コンダクタンスの半値幅を変化させる方法について論じている.負性微分コンダクタンスの半値幅がトランジスタの利得に依存することを初めて見いだし,回路応用に有利な半値幅の小さな負性微分コンダクタンス特性を得るための設計指針について述べている.

第5章は,「Control of Full Width at Half Maximum of Coulomb Blockade Oscillation in Silicon Single-Hole Transistors at Room Temperature」(室温動作シリコン単正孔トランジスタにおけるクーロンブロッケード振動の半値幅制御)と題し,極薄埋込酸化膜を有するSOI基板を用いてクーロンブロッケード振動の半値幅を基板バイアスにより変化させる新しい方法について論じている.実際にデバイスを試作し,半値幅の変調に室温で成功している.

第6章は「Conclusions」(結論)であり,本論文の結論を述べている.

以上のように本論文は,室温動作シリコン単電子・単正孔トランジスタの応用を目的として,離散準位を考慮したコンパクトモデリングを行うとともに,負性微分コンダクタンス制御およびクーロンブロッケード振動の半値幅制御を実験を通じて実証したものであって,電子工学上寄与するところが少なくない.

よって本論文は博士(工学)の学位請求論文として合格と認められる.