The fluctuating parameters which are considered to be the origins of threshold voltage (Vth) variation in metal-oxide-semiconductor field-effect-transistors (MOSFETs) are developed and introduced into three-dimensional device simulator. Using device simulation with new developed fluctuating parameters, it makes possible to evaluate the Vth variation in real devices. Each fluctuating parameter is assumed independently to see the impact on Vth variation more clearly.

In the past couple of years MOSFETs have reached decananometre (between 10 nm and 100 nm) dimensions with 40-50 nm physical gate length devices available now in the 45 nm technology node, 32 nm transistors ready for mass production in next couple years. The gate length of the most advanced MOSFETs has already fallen below 30 nm. However, various problems that obstruct more miniaturization of MOSFETs have become prominent as the device size is aggressively scaled down. The electrical characteristic variation, such as Vth variation is one of the big issues in scaling MOSFETs. To reduce the issue of Vth variation, its origin should be clarified first. This issue becomes prominent in short channel because the fluctuating parameters are not averaged out in small size MOSFETs.

The objective of this study is to analysis the origins of Vth variation of both NMOS and PMOS in current VLSI technology. Since, it is very complicated to determine the real origin of Vth variation in short channel due to the short channel effect (SCE) and drain induced barrier lowering (DIBL), this work is focused on not-so-aggressively scaled down gate length at low drain voltage. In cause analysis of the Vth variation, Takeuchi coefficient B(VT) is utilized, which is derived from uniformly random dopant fluctuation with low drain voltage. For estimating dopant profile effect on Vth variation, a new methodology is proposed. Using a newly proposed method, dopant profile effect on Vth variation is enhanced, so that profile impact can be observed clearly.

A very rapid method of estimating the effect of gate edge fluctuation on Vth variability in MOSFETs is proposed. An empirical model is developed, in which correlation width (Wc) from gate line width roughness (LWR) is a key parameter of the model. The validity of the model is confirmed using the measured data and an autoregressive model. Wc is extracted from the gate line edge shape depicted in a scanning electron microscope (SEM) image. This method is very useful for the intuitive understanding of the gate edge fluctuation effect on Vth variability.

Two well known dopant models for the Coulomb potential, which are atomistic model and long-range model, have been compared using device parameters in the 45nm technology node and beyond. It is found that the atomistic model has unacceptable dependences of average threshold voltage on mesh spacing and substrate dopant concentration, while the long-range model has minimum dependences. Consequently, the atomistic model severely overestimates the Takeuchi coefficient B(VT), which is one of the most important parameters for random threshold voltage variation. It is concluded that the long-range model is more suitable for the prediction of random variation in future aggressively scaled metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Vth variations induced by oxide thickness fluctuation (OTF) and local gate depletion (LGD) in MOSFETs are studied using classical three-dimensional (3D) drift-diffusion (DD) simulations. The models for both OTF and LGD are based on transmission electron microscope (TEM) observations. OTF is generated using random roughness steps at SiO2/Si interface and LGD is generated using random size and position of grains in poly-Si gate. The impact of both models on Vth variation is analyzed by the Takeuchi coefficient, B(VT). It is found that both OTF and LGD are not the main origin of Vth variation demonstrated by B(VT) analyses.

Randomness of discrete fixed charges at SiO2/Si interface of NMOS, which is thought to be one of the possible origins of threshold voltage (Vth) variation, is investigated using 3D device simulation. Three cases of fixed charge types are assumed; (i) both negative and positive sheet charges exist with zero net charge (mix charges), (ii) only negative sheet charges exist, and (iii) only positive sheet charges exist. B(VT) is used as a Vth variation indicator. It is found that, even if high concentration of fixed charge (10(12) cm(-2)) is assumed, the difference of Vth variation between measured NMOS and random dopant fluctuation model by 3D TCAD still can not be explained, which reveals that other fluctuated parameters exists.

Finally, a new methodology for evaluating dopant profile effect on Vth variability is proposed. Body bias coefficient is a key to the model used in this method. Using this method, pure random dopant fluctuation and its profile effect can be clearly observed.

本論文は,「Cause Analysis of Threshold Voltage Variability in MOSFETs by Device Simulation」(和訳:デバイスシミュレーションによるMOSFETのしきい値電圧ばらつきの要因解析)と題し,英文で書かれている.本論文は,MOSトランジスタのランダムな特性ばらつきの原因を三次元シミュレーションにより調べたもので,全9章より構成される.

第1章は「Introduction」(序論)であり,大規模集積回路を構成するMOS電界効果トランジスタの微細化にともない特性ばらつきの問題が顕在化した状況をまとめるとともに,特性ばらつきの原因となる種々の要因について述べており,本論文の背景と目的を明確にしている.

第2章は,「Gate Edge Fluctuation Effect on V(th) Variation」(ゲートエッジゆらぎがVthばらつきに与える影響)と題し,三次元シミュレーションを用いずにゲートエッジゆらぎがによる特性ばらつきをシミュレーションする新しいモデルについて述べ,モデルの実用性を実証している.

第3章は,「Impact of Oxide Thickness Fluctuation (OTF) on V(th) Variation」(酸化膜厚ゆらぎがVthばらつきに与える影響)と題し,ゲート酸化膜厚ゆらぎの効果を三次元シミュレーションに取り入れるモデルを開発し,ゲート酸化膜厚ゆらぎがVthばらつきに与える影響を解析している.

第4章は,「Impact of Local Gate Depletion (LGD) on V(th) Variation」(ローカルゲート空乏化がVthばらつきに与える影響)と題し,ローカルゲート空乏化の効果を三次元シミュレーションに取り入れるモデルを開発し,ローカルゲート空乏化がVthばらつきに与える影響を解析している.

第5章は,「Impact of Random Fixed Charge at SiO2/Si Interface on Vth Variation」(SiO2/Si界面のランダム固定電荷ゆらぎがVthばらつきに与える影響)と題し,ランダム固定電荷ゆらぎの効果を三次元シミュレーションに取り入れるモデルを開発し,ランダム固定電荷ゆらぎがVthばらつきに与える影響を解析している.

第6章は,「Consideration of Random Dopant Fluctuation (RDF) Models」(ランダム不純物ばらつきモデルに関する考察)と題し,ランダムな不純物分布の影響を三次元シミュレーションに組み込む際のモデルについて考察している.

第7章は,「Investigation of V(th) Variation Origins」(Vthばらつき原因の解明)と題し,これまでの章で行ったシミュレーション結果を先端MOSトランジスタの実測の特性ばらつき結果と比較することにより,Vthばらつきの原因を調べている.

第8章は,「A New Methodology for Evaluating Vth Variability Considering Dopant Depth Profile」(不純物の深さ分布を考慮したVthばらつきを評価する新しい方法)と題し,不純物の深さプロファイルによるVthばらつきの変化を正規化する新しい方法を提案し,実測とシミュレーションによりその方法を実証している.

第9章は「Conclusions」(結論)であり,本論文の結論を述べている.

以上のように本論文は,MOSトランジスタにおける各種ランダムばらつき要因が電気的特性ばらつきに与える影響に関するデバイスシミュレーションを行い,特性ばらつきの原因を解析するとともに,特性ばらつき原因の解明に有効な新しい正規化法を提案したものであって,電子工学上寄与するところが少なくない.

よって本論文は博士(工学)の学位請求論文として合格と認められる.