Real-time image recognition becomes quite important in various applications such as automotive control, robot vision, and so forth. For establishing an intelligent perception system in a power efficient manner, learning from biology and implementing the principle of biological mechanisms is a promising approach. In this reason, a directional edge-based associative processor architecture has been proposed. However, because edge detection is computationally very expensive, software programs running on general-purpose computers are not suitable to real-time and low-power performance. Therefore, it is required to develop dedicated VLSI hardwares for human-like robust image recognition systems.

The purpose of this thesis is developing CMOS vision sensors capable of performing intelligent image processing for human-like perception systems because directional edge detection consumes most part of the computation. For further flexibility of the system, it is necessary to enhance robustness against various kinds of environmental variations. In this point, multiple-resolution image processing in conjunction with the edge-based representation gives scale-invariant robust image perception. On the other hand, thresholding of edge-filtered images is quite important to detect only essential information from the images. In order to make the system compatible to such requirement, further advanced functions need be directly implemented on CMOS vision sensors.

Firstly, multiple-resolution directional edge filtering CMOS vision sensors have been developed for scale-invariant image recognition. A pixel-parallel self-similitude computation architecture has been proposed for multiple-resolution kernel convolutions based on focal plane image processing. The self-similitude organization has enabled pixel-by-pixel multiple-resolution image filtering with minimal complexity in interconnects. As a result, it has become possible to accomplish any (1/2)n-resolution directional edge filtering in (n+2) steps. Analog proof-of-concept chips using a switched floating-gate MOS technology were designed and fabricated in a 0.35-μm 3-metal CMOS technology, where only the line-parallel processing is carried out by applying the subtraction-separated configuration for enhancing the fill factor. The four-directional edge filtering at full, half, and quarter resolutions was demonstrated by chip measurements.

A non-subtraction configuration of the self-similitude image processing architecture has been developed for realizing full pixel-parallel multiple-resolution directional edge filtering. In contrast to the subtraction-separated configuration, subtraction operation has been entirely eliminated from the computation repertory of processing elements in the present configuration. As a result, hardware organization of the multiple-resolution edge filtering CMOS vision sensor has been greatly simplified. In addition, full pixel-parallel self-similitude processing has been established without any complexity in interconnects. An analog multiple-resolution directional edge filtering chip implemented using current-mode computation was designed and fabricated in a 0.18-μm 5-metal CMOS technology. The concept has been verified by chip measurements, which show that the four-directional edge filtering at multiple resolutions is accomplished at a rate of 910 frames/sec for 56x56-pixel images.

An edge detection CMOS vision sensor employing global thresholding operation has been developed. A cyclic-line-access computation scheme has enabled seamless directional edge filtering in a row-parallel manner. The global thresholding algorithm adaptively determines the threshold value by taking entire intensity distribution in the image into account and allows us to extract more significant features from input images autonomously. An analog proof-of-concept chip for four-directional edge detection was designed and fabricated in a 0.18-μm single-poly 5-metal CMOS technology. The concept has been experimentally verified by measurements of fabricated chips, where the chips show more than 3.4x104 times better performance than that of CPU computation.

In this thesis, we have proved the capability of CMOS vision sensor technologies in conjunction with analog computation, where the vision chips are able to carry out various kinds of advanced image processing. The efficiency is much better than that of the general-purpose processors, and the low-power and real-time computation contributes to performance enhancement of the human-like recognition systems.

本論文は,Analog Feature-Extraction CMOS Vision Sensors for Edge-Based Image Recognition Systems(和訳:エッジ情報に基づく画像認識システムのためのアナログ特徴抽出CMOSビジョンセンサー)と題し,人間のように柔軟な画像認識処理実現を目指し,その基本となる画像のエッジ情報抽出のためにCMOSイメージセンサーの新たなアーキテクチャを提案するとともに,そのアナログ回路実現に関する研究成果を纏めたもので,全文5章よりなり英文で書かれている.

第1章は,序論であり,本研究の背景について議論するとともに,本論文の構成について述べている.

第2章は,Multiple-Resolution Edge-Filtering Analog Vision Sensors Employing the Pixel-Parallel Self-Similitude Processingと題し,スケールに依存しない画像認識を実現するための多重解像度イメージセンサーについて述べている.多数の近傍画素データを用いて行う演算を同時並列に実行しなければならないため,非常に複雑な配線構造が必要となるが,「自己相似演算」と呼ぶ新たなアーキテクチャを提案することによりこの問題を解決している.近傍4画素データの加算・減算をフラクタル的な構造を用いて順次大きな領域へ自己再帰的に拡張していくことにより,(1/2)n倍の解像度の演算をn+2ステップの並列演算で実現するユニークな方法である.0.35μm CMOS技術を用いて64×64ピクセルサイズのCMOSイメージセンサーチップを試作,その計測により有効性を実証した.このチップは,フローティング・ゲートMOS回路技術を用いた電圧モード演算を採用し,回路規模の比較的大きな減算器をイメージセンサーアレーから分離配置することにより,効率の良い行並列演算を実現している.

第3章は,A Non-Subtraction Configuration of Self-Similitude Architecture and its Current-Mode Implementationと題し,前章で開発した自己相似演算を全画素並列で実行できる新たな構成方法について述べている.前章の方式では,並列演算のための各演算回路は加算・減算両方の機能を必要としたが,本章で提案する方式では画素信号自身に正・負の符号を付与することにより,加算演算のみでの実装を可能にしている.電流演算方式の回路を採用し,0.18μm CMOS技術を用いて56×56ピクセルサイズの多重解像度CMOSイメージセンサーチップを設計,等倍,1/2,1/4の3つの解像度における4方向のエッジフィルター処理を,毎秒910フレームという高速で実行できることを試作チップの実測により示した.本方式では,各画素の値に正負の符号を様々なパターンで割り振ることにより,より一般的なフィルター演算に関しても多重解像度で全画素並列処理が実現できる.これは,新たに提案した「自己相似演算アーキテクチャ」が,さらに多様な発展性を持っていることを示した重要な研究成果である.

第4章は,A Row-Parallel Cyclic-Line-Access Edge Detection CMOS Vision Sensor Employing Global Threshold Operationと題し,4方向のエッジフィルター処理を行った画像データに対し,適応的な閾値処理を施すことにより重要な特徴のみ選択的に抽出することのできるCMOSイメージセンサーの開発について述べている.4方向のフィルター処理を行った各画素データに対し,全画素並列にランクオーダー演算を行い,重要度の高い順に所定の数のエッジ情報を残す.70×68ピクセルサイズのイメージセンサーチップを0.18μm CMOS技術を用いて設計・試作し,チップの測定によりその有効性を実証した.

第5章は結論である.

以上要するに本論文は,人間のように柔軟な画像認識システム実現を目指し,その最も基本となる画像の特徴抽出に関し,これを多重解像度で実行できる「自己相似演算アーキテクチャ」を新たに提案するとともに,これを並列演算によって実現する様々な回路方式を開発,実際にCMOSイメージセンサーチップを設計・試作・評価し,その有効性を実測結果によって実証したもので,情報学の基盤に寄与するところが少なくない.

したがって,博士(科学)の学位を授与できると認める.