In the past several decades, the size of a metal-oxide-semiconductor field-effect-transistor (MOSFET), the basic element in very-large-scale integrated circuits (VLSI), has been scaled down for higher integration and higher performance. As of 2012, the gate length of MOSFETs has reached a sub-30 nm regime. However, as the scaling proceeds, several problems stand out and prevent more miniaturization of MOSFETs.Among all the issues arise to handicap the continuous device scaling, two issues are with most great importance, one is the short channel effect (SCE), and the other is the variability.

To curb the short channel effect, devices with multiple gates have been developed to improve the gate-channel controllability for better electrical characteristics with the progress in nano-scale fabrication technology. Among all the promising post-CMOS structures, the Silicon nanowire MOSFETs, have attracted much attention with their high immunity to short-channel effect for a promising candidates for future VLSI technologies with high performance in recent year. In actual applications, we care about the devices performance, such as ON/OFF drive current and operation speed; however, the underlying physical mechanism is the carrier mobility in the transport channel. Most of the experimental works on mobility in silicon nanowires are carried on with either indirect extraction method or special structure (for example, multiple nanowire array) to circumvent the difficulty originated from the ultra-small size of the silicon nanowire. The intrinsic carrier mobility of single nanowire is still in the dark.

Along with the rapid device scaling, the variability turns to be one of the critical concerns. Threshold voltage (VTH) variability considerably degrades the stability of integrated circuits. The minimum operation voltage (Vmin) in logic circuits is limited by device variability, and static random access memory (SRAM) fails at a low supply voltage owing to transistor unbalance in a cell. It is now mandatory to take this variability into consideration in circuit design to maintain a high yield. It is known that random dopant fluctuation (RDF) is the dominant origin of random VTH variability in conventional bulk MOSFETs. Recently, it is reported that the variability of both DIBL (drain induced barrier lowering) and COV (current-on-set voltage) is also caused by RDF and leads to instability of SRAM cells and drain-current variability. It is shown that intrinsic channel fully depleted (FD) silicon-on-insulator (SOI) MOSFETs have not only a smaller VTH variability but also smaller DIBL and COV variabilities owing to the absence of RDF. However, the DIBL and COV variabilities still remain, possibly owing to the variability of workfunction in the metal gate electrode, and further reduction of variability is strongly required for better circuit performance variability and SRAM stability. The variability in silicon nanowire MOSFETs should be studied to investigate the variability mechanism for the possibility of further variability suppression.

The purpose of this work is to evaluate the potential of silicon nanowire MOSFETs for promising "More Moore" device in terms of both device performance enhancement and stability improvement. In this work, silicon nanowire FETs with various designs are extensively studied for carrier mobility and variability. This work is based mainly on the experiments including device design, sample fabrication and characteristic measurement.

In this paper, on the base of split C-V method, experimental and theoretical investigations of carrier mobility characteristics in single silicon nanowires are described systematically for the first time. It is found that side surface orientation plays the key role that determinates the mobility modulation in narrower nanowires, as well as the surface roughness.

And, it is experimentally found that within-device variability of not only VTH but also those of DIBL and COV is suppressed in intrinsic channel nanowire FETs owing to the non intentionally doped channel and the absence of gate workfunction variability. The intrinsic channel silicon nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression.

本論文は,「A Study of Carrier Mobility and Variability in Silicon Nanowire MOSFETs」(シリコンナノワイヤMOSFETにおけるキャリア移動度と特性ばらつきに関する研究)と題し,英文で書かれている.本論文は,将来の大規模集積回路向けトランジスタとして期待されているシリコンナノワイヤトランジスタにおけるキャリア移動度と特性ばらつきを論じたものであって,全6章より構成される.

第1章は「Introduction」(序論)であり,トランジスタの微細化に伴い従来のトランジスタ構造をナノワイヤ構造へ変えることの意義と,キャリア移動度と特性ばらつき抑制の重要性をまとめており,本論文の背景と目的を明確にしている.

第2章は,「Fundamentals of Carrier Mobility in Silicon Nanowire MOSFETs」(シリコンナノワイヤMOSFETにおけるキャリア移動度の基礎)と題し,ナノワイヤトランジスタにおけるキャリア移動度のデバイス物理とその測定法の問題点について述べている.

第3章は,「Carrier Mobility in Single Silicon Nanowire MOSFETs」(シリコンナノワイヤMOSFETにおけるキャリア移動度)と題し,単一のナノワイヤトランジスタのキャリア移動度を正確に測定するためのナノワイヤ構造設計および測定法について述べ,ナノワイヤトランジスタの移動度がワイヤ幅が狭くなるほど小さくなることを示すとともに,p型ナノワイヤトランジスタにおいて移動度がユニバーサル移動度より大きくなることを明らかにしている.

第4章は,「Analysis of Carrier Mobility in Silicon Nanowire MOSFETs」(シリコンナノワイヤMOSFETにおけるキャリア移動度の解析)と題し,低温における移動度測定の結果から,ナノワイヤ幅が細くなるほど移動度が低下する原因が,ナノワイヤの側面チャネルにおける表面ラフネス散乱であることを明らかにしている.

第5章は,「Variability in Silicon Nanowire MOSFETs」(シリコンナノワイヤMOSFETにおけるばらつき)と題し,従来のバルクMOSトランジスタや完全空乏型SOI MOSトランジスタと比較して,シリコンナノワイヤトランジスタではデバイス内の特性ばらつきが極めて小さくなることを明らかにしている.

第6章は,「Conclusions」(結論)であり,本論文の結論を述べている.

以上のように本論文は,将来のデバイス構造として期待されるシリコンナノワイヤトランジスタにおいて,単一のナノワイヤトランジスタのキャリア移動度を正確に測定する手法を確立し,移動度を決定する機構を明らかにするとともに,特性ばらつきが抑制されることを実験により示したものであって,電子工学上寄与するところが少なくない.

よって本論文は博士(工学)の学位請求論文として合格と認められる.