Integrated circuits （ICs） have advanced remarkably during the past 35 years and today an IC usually have more than one million transistors, called large scale integrated circuit （LSI）. LSI can be found in computers, cellular phones and other digital appliances that exit everywhere. LSI has become absolutely necessary in people life, become indispensable element to realize the ubiquitous society. LSI is expected to continue progress more and more, but coming to these days it faces some problems such as power consumption, development time and cost, process variation, etc. In the state-of-the-art technology, power dissipation of one high-end processor exceeds 100 W, and leakage power accounts for more than 50% of total power. Many methods such as clock-gating, dual-VDD, dual-VTH, MTCMOS （Multi-threshold CMOS）, VTCMOS （Variable Threshold CMOS）, Super Cut-off CMOS, Super Cut-off Zigzag CMOS, VDD hopping, etc. have been proposed to reduce power consumption, especially leakage power. Thanks to these techniques, power consumption of LSI has been reduced to a degree that can be accepted for now. However, to make the progress of LSI continue in the next ten years, to secure the device reliability and to extend the battery life of mobile devices, more two orders of magnitude reduction of power consumption is assumed to be necessary. Another problem is the development time and cost. The development time and cost have increased explosively and today they could be more than one year and one million dollars, respectively. In order to solve the development time and cost issue, some programmable LSIs such as FPGA, reconfigurable processor, etc. have been proposed. The programmable LSIs usually have more transistors than other LSIs in order to achieve the programmability. Therefore, they consume more power than the others. In this thesis, low-power especially low-leakage circuit design methods with the application to FPGA are investigated.

First, low-power high-speed level shifters are proposed. In the proposed level shifters, because the contention between the pull-up transistors and pull-down transistors is mitigated, the crow-bar current becomes smaller. Therefore, power and delay are smaller than that of the conventional level shifter. The measurement results when 0.35〓m CMOS technology is used, shows that power and delay can be reduced by 50% and 65%, respectively.

Second, the basic logic element of an FPGA, CLB （Configurable Logic Block）, with low-leakage current is proposed. In the proposed CLB, sneak leakage issue is dealt. Simulation using 0.15〓m CMOS technology shows that leakage current of the proposed is reduced by two orders compared to that of the conventional CLB.

Next, low-leakage low-power FPGA architecture is proposed. In the proposed FPGA, low-swing interconnect and the proposed level shifter, CLB are adopted. Four CLBs are clustered into one block. A test chip fabricated in 90nm CMOS technology shows that dynamic power of the proposed FPGA can be reduced by 82% compared to that of the conventional FPGA when the speed is half of the achievable maximum speed. Leakage power of the proposed FPGA can be reduced by 89%.

Finally, a CAD for low-power FPGA is proposed. VPR is the commonly used CAD for studying FPGA architecture but it does not have a model to estimate power consumption of FPGA. A power model has been proposed by a group from the University of British Columbia called UBC Power Model. This model is included in the VPR and can be used to investigate many kinds of FPGA which have the island style architecture. However, the UBC Power Model is for only FPGAs with a single supply voltage. A new CAD that available for the use of dual-VDD, low-swing interconnect, Zigzag power-gating and level shifter is proposed. Simulation using the proposed CAD with MCNC benchmark circuits shows that, power consumption of the proposed FPGA which includes dual-VDD, low-swing interconnect, Zigzag power-gating and level shifter can be reduced by 57.4% on average.

本論文は「Low-power Nano-meter CMOS Circuit Designs with Application to FPGA」（和訳：低電力ナノメートルCMOS回路設計とそのFPGAへの応用）と題し、将来のユビキタス・エレクトロニクス環境を支えるシリコンの低消費電力回路技術を提示するもので、全7章で構成されている。

第1章は「Introduction」（序論）であり、近年のユビキタス社会を支える半導体集積回路の問題点である消費電力・設計期間・設計コストついて述べ、これらの問題を解決する必要性を説き、本論分の目的と背景を明確にしている。

第2章は「Low Power Techniques and Issues of the Conventional FPGA」（低消費電力技術と従来のFPGAの問題点）と題し、シリコンVLSIの従来の消費電力技術とFPGAの問題点について述べ、今後のシリコンVLSIの消費電力を削減するにはどうのような技術が必要であるかについて記述している。

第3章は「Low-power High-speed Level Shifters」（低消費電力・高速レベル・シフタ）と題し、複数の電圧が混在する領域内での電圧間の変換を行うにはレベル・シフタという回路が不可欠である。レベル・シフタについて問題点である信号の衝突を示し、衝突を緩和する新しいレベル・シフタを提案した。衝突を緩和することによって低消費電力かつ高速のレベル・シフタを実現でき、シミュレーションと実験により実証し、有効性を確認した。

第4章は「Low Power FPGA Basic Cell」（低消費電力FPGAの基本セル）と題し、FPGAの基本ロジック・セルであるCLB（Configurable Logic Block）の低消費電力設計について述べるとともに、シミュレーションを用いて実証し、有効性を示した。

第5章は「Low Power FPGA Architecture and Circuit」（低消費電力FPGAのアーキテクチャと回路）と題し、低電力を実現するために新しいFPGAのアーキテクチャと回路を提案した。シミュレーションと実験により提案したFPGAは従来なものに比べてダイナミック電力とリーク電力はそれぞれ82%と89%を削減できた。

第6章は「CAD for Low-power FPGA」（低消費電力FPGAのCAD）と題し、低消費電力FPGAの設計に必要な消費電力を解析するCADについて述べる。既存のFPGA CADは第5章で提案したFPGAアーキテクチャを解析できないため改良する必要がある。改良したCADでベンチマーク回路を用い、シミュレーション結果から提案したFPGAのメリットである低消費電力を確認した。

第7章は「Conclusions」（結論）であり、本論文の成果を要約し結論を述べるとともに、本論文の学会や産業界に対する貢献についても触れている。

以上のように本論文は、ユビキタス・エレクトロニクスの基礎となる、シリコンをベースとしたCMOS回路の低電力設計手法と、具体的にFPGAへの応用を示すとともに、その有効性を設計・試作・測定を通じて実証したものであって、電子工学上寄与するところが少なくない。

よって本論文は博士（工学）の学位請求論文として合格と認められる。