Abstract:

Signal integrity has become a more serious issue as VLSI's scaling of technology continues into deep sub-micron region. While scaling of transistors results in faster yet low-power circuits, shrinking the physical size of interconnect may restrict VLSI's performance. Previously neglected interconnect inductance seems to have become the cause of various signal integrity issues such as propagation delay error, overshoots, and crosstalk due to coupling effects. In this dissertation, the behaviors of inductive interconnects are investigated.

First, modeling of single and parallel VLSI's interconnects are employed. Output response of single inductive interconnect is modeled. An approximation function of the model is proposed in quadratic delayed transfer function. Using proposed approximation function, which is able to be transformed to closed-form time domain function analytically, the voltage waveform of inductive interconnects can be calculated simply. It is also shown that by transformation of variable, proposed approximation function can be expressed using only one parameter, A. Interconnects are less inductive or behave as RC interconnects when A is less than 1. Otherwise, inductive effect may need to be considered. Moreover, formulas of the peak of overshoot time and voltage, as well as attenuation constant and peak-to-peak time are also derived in very simple forms. Also, a closed-form propagation delay formula is proposed. Additional study about distributed model of interconnect is also given.

Furthermore, the study is extended to modeling of parallel interconnects. The case of two adjacent interconnects, which consist of aggressor and victim lines, with inductive and capacitive coupling is studied. Output responses of two-adjacent coupled interconnects are modeled into two transfer functions, so-called fast and slow waves. Aforementioned proposed approximation function is applied for fast and slow waves. Finally, closed-form functions of output responses of both aggressor and victim lines are calculated with the summation and difference between the fast and slow waves.

The second part of this dissertation is discussing the effects of inductive effects in deep sub-micron region as well as in the previous technologies. The trends of inductive effects in deep sub-micron VLSI's are studied for the optimal buffered interconnect by investigating the propagation delay deviation, output response, and power consumption distribution. In optimal buffered interconnect, big driver and long enough line are used to make interconnect more inductive. The study shows that global layers interconnects, which lay on the upper layers, suffer from inductive effects much more than local layers interconnects, which are close to the cells of transistors. Also, it is known that inductive effect increases as interconnect width increases. For optimally buffered interconnects, error due to inductive effects is less than 10% in 90nm-technology, when interconnect width is less than five times of minimum interconnect width, and the error decreases as scaling of technology continues. Furthermore, the trend of maximal value of inductive index for past, present, and future technologies are calculated from the past 1.2μm-technology to the future 22nm-technology. The result shows that previously inductive effect was neglectable but had been increasing until before entering deep sub-micron region. Later, the inductive effect is gradually decreasing in more advanced technologies. This trend explains why previously VLSI's designers did not consider inductive effects, while from this study on inductive effects in optimally buffered interconnects, the effects are gradually decreasing in deep sub-micron VLSI's.

Finally, to verify the signal integrity issues in the VLSI's, measuring the characteristics of on-chip interconnects is required. However, measuring the waveform on the lower-level interconnects from the outside of the chip encounters many difficulties due to the higher-level metals that block the access to the lower-level metals physically and electrically. Thus, an on-chip sampling oscilloscope with very high time resolution is proposed for measuring the waveforms of interconnects. Proposed on-chip sampling oscilloscope is designed and fabricated in 90nm-technology. Measurement of interconnects waveform is then demonstrated with smoothly adjustable 1ps-to-64ps time resolution, which is enabled by sampling timing generator based on ramp waveform division scheme.

本論文は「Modeling and Characterization of Electrical Behaviors of Interconnects in Deep Sub-micron VLSI's」（和訳：ディープサブミクロンVLSIにおける配線の電気信号特性とそのモデリングに関する研究）と題し、インダクタンスの効果を考慮したVLSIにおける配線の電気信号特性のモデル化とインダクタンスの効果を観測するためのオンチップ・サンプリング・オシロスコープの方式を提示するもので、全5章で構成されている。

第1章は「Introduction」（序論）であり、近年VLSI内配線におけるシグナル・インテグリティ劣化の要因の一つとして注目されている配線のインダクタンスの効果による問題をまとめることにより、本論文の目的と背景を明確にしている。

第2章は「Modeling of Single and Parallel Inductive Interconnects」（インダクタンスの効果を考慮した単独配線及び並列配線のモデル化）と題し、初めにインダクタンスの効果を考慮した単独配線のモデル化を行い、遅れ付き2次の伝達関数による近似手法を提案している。この近似手法を用いて、電圧波形、遅延時間、オーバーシュートの時刻と波高、減衰率、周期などを計算するための簡便な式を導出し、実用的なパラメータ範囲で近似度が十分であることを明らかにしている。また単独配線のインダクタンスの効果を評価するための指標を提案しており、これによってインダクタンス効果が無視できるかどうかを判断できる。更に、キャパシティブ・カップリングとともにインダクティブ・カップリングを有する並列配線の特性を計算するための式を導出している。

第3章は「Trends of Interconnects in Deep Sub-micron VLSI's」（ディープサブミクロンVLSIにおける配線のトレンド）と題し、インダクタンスの効果が出やすい大きなバッファと十分長い配線がある状況で遅延を最小化した際、配線幅が最小線幅の5倍以下である限りインダクタンスの効果が無視できることを示している。また、最小線幅の配線において、過去インダクタンスの効果が認識されてこなかったものの、微細化技術の進歩によってインダクタンスの効果が増加し、現在の90nm世代でピークに到達、今後更に微細化が進むにつれて再びインダクタンスの効果が減り、将来は無視できるとの予測を述べている。

第4章は「On-chip Sampling Oscilloscope for Signal Integrity Study」（シグナル・インテグリティを観察するためのオンチップ・サンプリング・オシロスコープ）と題し、シグナル・インテグリティを観察するためのオンチップ・サンプリング・オシロスコープに用いられる分解能測定回路の提案・設計・実測について述べている。

第5章は「Conclusions」（結論）であり、本論文の成果を要約し結論を述べている。

以上のように本論文は、VLSI上の配線特性をインダクタンス効果を含んだ形で表現できる見通しのよいモデルを提案し、そのモデルを用いて配線遅延や電圧オーバーシュートなどの簡便な表式を導出するとともに、その式を用いてインダクタンス効果の将来動向を明らかにしたもので、電子工学上寄与するところが少なくない。

よって本論文は博士（工学）の学位請求論文として合格と認められる。