Abstract:

　In the past, noise was not such a big issue in digital integrated circuits. However, the continuous progress in semiconductor technology put the noise issue among the major concerns of digital CMOS IC designers. This study concerns with the noise immunity of static CMOS low power digital design by investigating the noise immunity of the current low power static CMOS design schemes and presenting a fast and accurate methodology to evaluate the noise sensitivity of the different nodes in a design during the design phase. In addition, for the modeling/characterization of noise in digital circuits, techniques to measure the non-periodic noise and sensing the peak minimum/maximum fluctuation on-chip have been presented. The study is presented in five chapters in addition to conclusion.

　The first chapter includes a background about the power consumption and noise issues in current and future VLSI/ULSI digital design. It also includes the objectives of the study and thesis organization.

　In chapter two, we present the effect of noise on the performance of a selected group of low power as well as traditional digital design techniques. First, we present a model for the different noise sources in the digital circuits. Then we applied the model to a selected group of low power and traditional designs as testing circuits. The noise immunity of the tested schemes has been reported in terms of logic error and delay error. At the end of the chapter, we present a methodology for leakage power saving and at the same time has high noise immunity. One of the ways to increase the noise immunity of a digital circuit is to give special strengthen considerations to the soft (weak) parts (nodes) against noise. Since it is time consuming to analyze the noise-sensitivity of different nodes in a big design using transistor level simulators, an analytical (fast and accurate) method is required.

　In chapter three, we present a methodology to evaluate the noise-induced logic error probability in a given CMOS digital design in terms of supply voltage, threshold voltage, noise level and circuit configuration. At first, we modeled the noise immunity of the different logic gates in terms logic error probability including the effect of supply and threshold voltage, which is called electrical masking. Then, time masking has been modeled to include the variation of the spurious pulse width and generation time in the overall logic error probability. Moreover, the logic masking effect has been also considered. The electrical, timing and logic masking have been combined to form the overall logic error probability model. The model has been used to evaluate the logic error probability caused by the noise at the different nodes in digital circuit examples. The model results have been compared with results obtained from HSPICE simulation. The results reveal that the model fit with the expected simulation results achieving speedup factor of more than 1000 over HSPICE. Moreover, the calculation time of the methodology is linearly proportional with the number of gates in a design, and hence, the method is suitable for investigating the noise immunity of the big circuits. The model can be used to identify the weak parts against the noise in a given design during the design phase and hence it helps the designer in giving specific design considerations to strengthen the weak nodes. The methodology is based on hypothetical noise distribution. So that, for more accurate results, a real noise distribution should be provided.

　In chapter four we present, first, an overview on the previous works regarding the on-chip noise measurement has been given. To avoid the problems attached with the previous designs, an on-chip noise detector has been designed and fabricated using 0.18μm technology. The detector can detect the single-event or the non-periodic signals within the measurement time window. It is equipped with a programmable voltage divider to be able to detect high-swing signals having maximum theoretical frequency of 5GHz. The bandwidth of the output signal can be controlled by the user to fit the monitoring tools capability off-chip and to avoid the effects of the on-chip parasitic elements and hence conventional equipments can be used to measure the signal off-chip. Moreover, the detector is synthesizable and the designer can flexibly adjust its main parameters. A test chip is fabricated and tested successfully. The detector's design has been modified to increase the sampling rate. Upon the simulation results, the modified version is capable to measure signals of frequency (theoretically) up to 10GHz.

　Chapter five includes the description of a CPU-interfaced system to monitor the minimum/maximum fluctuation in both VDD and ground in a design. In addition to the magnitude information, the system has the ability to report the timing and spatial information of the spurious pulse. The system is designed using Rohm 0.18μm technology. The fluctuation is detected by comparing with a reference voltage supplied form off-chip, and the fluctuation information is send off-chip in digital format. The detector is simple, therefore, it can be replicated within a design to detect the fluctuations on VDD/Ground net at different spots and hence, safe operation can be guaranteed. The detector is interfaced by a CPU and hence it is suitable for future VLSI/ULSI circuits.

　Finally, we conclude the study in chapter six.

　本論文は「Study on Noise Immunity of Low-Power Static CMOS Digital Design(低電力スタティックCMOSデジタル設計におけるノイズ耐性に関する研究)」と題し、低電源電圧化が進む微細デバイスCMOS低消費電力デジタル回路で問題が顕著になりつつある回路のノイズ耐性およびノイズ特性について研究したもので、英文で記述され六章より構成されている．

第一章はIntroduction(序論)であり、研究の背景となっている将来の集積回路での電力消費と動作信頼性の問題を述べ研究の目的を明らかにしている。

　第二章は「Noise Immunity Investigation of Low Power Scheme (低消費電力回路方式のノイズ耐性の検討)」と題し、低消費電力向け回路方式として現在提案されている諸方式を対象として、電源雑音、信号配線雑音、素子バラツキを考慮したノイズ耐性について、数値シミュレーションによる検討を加えている。これに基づき将来予想される動作条件下でのノイズ耐性についての相対比較を行うとともに、新たに高ノイズ耐性回路方式(DVTMTCMOS)を提案しその効果を論じている。

　第三章は「Statistical Model for Logic Errors in CMOS Digital Circuits (CMOSデジタル回路における誤動作の統計的モデル)」と題し、解析的手法によりノイズ環境下でのCMOSインバータ回路の誤動作確率を解析的に計算するモデルを提案している。それをもとに低消費電力向けに提案されている諸回路方式のノイズ耐性を解析モデルにより比較検討するとともにシミュレーション結果と照合することでモデルの精度を検討している。この解析モデルを一般の論理ゲートに拡張応用するとともに、遅延と論理動作を考慮した多段論理回路での誤動作伝搬のモデルを提案し、回路としての誤動作確率の統計的解析方法を提案し、幾つかの回路について適用して数値シミュレーション結果と照合することで提案モデルの妥当性を明らかにしている。

　第四章は「On-chip Noise Measurement (雑音のオンチップ測定)」と題し、実際の微細加工技術を用いたCMOS論理回路を対象として雑音パラメータを求めるための手段として、電源波形をチップ上で記録・観測するための測定回路について研究した結果を述べている。電源は高速の過渡現象である電源雑音を記録するためのレベルシフター、サンプラー、マルチプレクサー、アナログ記憶、タイミング生成回路等から構成されており、高速過渡現象を時間変換した低速過渡現象としてチップ外に出力する機能を有しており、チップ試作実験を通してその実現性と有効性を示している。また回路固有の固定パターンノイズ等について検討を加え、その解決手法についても述べている。

　第五章は「On-chip Minimum/Maximum Fluctuations Detection(オンチップ最小/最大電圧変動検出)」と題し、CMOS論理回路が誤動作なく動作することを保証することを目的として電源電圧変動が許容範囲内であることを常時監視するためのモニター回路方式について検討した結果を述べている。チップ上にマトリクス状に並べられた最大値/最小値検出回路とその値が規定の範囲を逸脱した際に発生する警告信号を伝達する回路、および関連のタイマー回路等から構成されており、回路シミュレーションにより提案回路が機能することを示している。

　第六章は「Conclusion (結論)」であり本論文の研究成果をまとめている．

　以上、本論文は低消費電力向けに提案されている各種のCMOS論理回路方式を対象として、ノイズ耐性の観点から数値的および解析的モデルにより評価する手法を研究し、ノイズ耐性に優れた新たな回路方式を考案するとともに、実際の微細CMOS回路でのノイズ特性パラメータ観測と雑音許容変動範囲観測のための新しいオンチップモニタ回路を試作・研究したもので電子工学の発展に寄与する点が少なくない．

　よって本論文は博士(工学)の学位請求論文として合格したものと認められる．