Power integrity and power consumption have become a more serious issue as LSI's scaling of technology continues into nanometer region. While scaling of transistors results in faster yet low-power circuits, increased power supply current causes problem of switching for saving power consumption, which restricts the power efficiency of LSI's. Furthermore, systematic or random variations induced by its design and process result in excessive margin and higher power consumption. To cope with this problem, an adaptive noise canceller and global power optimization scheme is proposed and investigated.

The thesis is organized into 6 chapters. The first chapter describes trends and problems in nanometer CMOS LSI's as the background. Along scaling, the operation speed increases, on the other hand, leakage power does not scale well in nanometer CMOS LSI's, and process variation increases along scaling, which leads to large margin to obtain enough yield. To reduce cost and power consumption, adaptive control of supply and threshold voltage is essential because these post-Si tuning technologies do not only reduce the power consumption but also improve the yield, which lead to cost reduction.

Chapter 2 introduces conventional low-power techniques for system-on-chip (SoC) systems. This includes time-domain fine-grained adaptive controls and area-domain fine-grained adaptive controls. Time-domain control is to adaptively change the supply voltage or to switch the supply voltage of specific circuit block to reduce leakage when it is not in operation and preserve performance when in operation. Various sophisticated controls are available, though they have problem of switching noise to the supply line. This problem is treated in Chapter 3. Area-domain control is used to compensate process variation using frequency monitor and back-bias generating circuit. Conventional control of this type has large area overhead due to the bias generator, and within-die process variation is becoming more random along process scaling, which makes it difficult to implement. A solution to this is shown in Chapter 4.

Chapter 3 proposes novel power supply line noise canceller using higher voltage supply for supply voltage droop in wake-up. Proposed canceller uses additional higher-than-VDD power supply, namely VDDH, to allow more current flow through restricted power supply network, which enables to cancel the noise without large wire or power supply network overhead. Moreover, optimum control of the switch between VDDH and VDD, and the amount of the noise cancelling current are discussed. With noise cancelling current as large as the load current and slow turn-off, the canceller is stable and optimum cancelling effect is achieved.

To optimize the power consumption of CMOS LSI's, not only dynamic control of the supply voltage or switching the circuit to reduce leakage, but also coping with within-die variation to reduce excessive margin which consumes excessive power is essential. Chapter 4 proposes a fine-grained global threshold voltage optimization scheme for digital circuit. Nanometer CMOS LSI's have not only random variation but also systematic variation, which derive from both design and process variations. By dividing the circuit into blocks and applying different body-bias voltages for each blocks, both systematic variations can be cancelled. This means digital circuits have some not necessary fast part and necessary fast part, and to drive the first part in fast mode consumes excessive power. The principle and detailed design consideration and flow are also described in this chapter.

In chapter 5, a power gating switch with MEMS technology is presented. Conventional power gating switch with CMOS technology has finite leakage current, which becomes problem especially for very low power systems. With the MEMS switch, leakage current can be cut to almost zero, though the on-resistance of the fabricated chip is high. From this, the MEMS switch is for very low power systems which can accept kΩ order of on-resistance and which cannot accept on/off ratio as low as 105. Furthermore, the durability of the MEMS switch is discussed in this chapter, and a circuit technology to extend its life time is also presented.

Finally, the thesis concludes in chapter 6.

本論文は「Optimization of Nanometer CMOS LSI's through Adaptive Control of Supply and Threshold Voltage」(和訳:電源電圧としきい値電圧制御によるナノメートル CMOS LSIの最適化)と題し、今後の集積回路に要求される特性を考察するとともに、細粒度で電源および基板バイアスを調整することで、面積や遅延などのオーバーヘッドをあまり増すことなく、より低消費電力やより安定な動作を実現する手法を提示するもので、全6章で構成されている。

第1章は「Introduction」(序論)であり、今後のより高い集積度を持つ集積システムに向けた低消費電力化技術の課題について述べるとともに、本研究の背景を述べ、目的を明確化している。

第2章は「Conventional low power techniques for system-on-chip (SoC) systems」(従来のシステム・オン・チップシステム用低消費電力化技術)と題し、従来の動的電源電圧制御や基板バイアスなどによる性能最適化技術の動作原理、課題等について考察し、関連研究について概説している。

第3章は「An on-chip noise canceller with high voltage supply lines」(高圧電源線を用いたオンチップノイズキャンセラ)と題し、動的低消費電力化制御の弊害として発生する電源ノイズの要因と電源配線による影響を明らかにし、電源ノイズを発生させるスイッチングの際に電源電圧より高い電圧を供給する配線から一時的に電流を供給することにより電源ノイズを低減する手法を提案。90nmCMOS論理回路に本手法を適用した場合にノイズの68%低減をチップ試作を通じて実証。更に安定動作を実現する条件についての設計論を確立し、提案手法の実装を容易なものとした。

第4章は「Power reduction by fine-grained global optimization of threshold voltages with back-biasing」(基板バイアスを用いたしきい値電圧の細粒度かつ大局的な最適化による消費電力の低減)と題し、論理回路に存在するシステマチックなばらつきを、面積や遅延などのオーバーヘッドをあまり増すことなく、製造後に補正する手法を提案。90nmCMOSにおいて1Mゲート規模の論理回路に適用することで18%の消費電力低減を実証した。また、設計手法および最適化手法について検討し、テスト時間の大幅な増加なしに最適化を行う手法を提案した。

第5章は「MEMS power gating switch for reducing standby power」(MEMSパワーゲーティングスイッチを用いたスタンバイ電力の低減)と題し、パワーゲーティングのスイッチングトランジスタをMEMSスイッチに置換することでスタンバイ電力を低減する手法を提案、トランジスタに比べて800倍のオンオフ比を持つスイッチを駆動する回路設計技術を設計、試作を通して確立した。

第6章は「Conclusions」(結論)であり、本研究の成果を要約し結論を述べている。

以上のように本論文は、ナノメートルCMOS LSIにおいて、電源の動的制御によって電源線のノイズを低減するノイズキャンセラ、基板バイアスの細粒度制御によって設計ばらつきを補正する最適化手法、及び電源をMEMSスイッチで制御してスタンバイ時の電力を低減する方式を提案するとともに、チップ試作、実測を通してその効果を実証したもので電子工学上寄与するところが少なくない。

よって本論文は博士(工学)の学位請求論文として合格と認められる。