Associative processing or template matching plays an important role in computational scheme in intelligent information processing. Because such a process is computationally very expensive and time-consuming, it would be better if this process is carried out by dedicated VLSI associative processors rather than programs running on a general-purpose computer. Generally, the associative processor is a maximum-likelihood search engine having a huge cache memory for past experience or knowledge and a parallel search architecture. In this thesis, several analog VLSI associative processors have been developed for a variety of purposes of intelligent information processing.

Recently, nanoscale devices have attracted much attention because of its ability in terms of enhanced integration density and ultra low-power consumption. Resonance characteristics are typical inherent non-linear characteristics observed in such devices. There would be a great opportunity for building large scale intelligent systems if we could use such kind of characteristics directly in computation. In addition, as devices at the nanoscale have a higher probability of being defective than conventional CMOS devices, designing reliable circuits with such devices is a major challenge. Thus nanoscale devices are more suitable for building majority-decision-making systems like the operation of associative systems than building logic functions. However, nano devices are still in the research phases, and most demonstrations have been just achieved at the device level or simple circuitry. The work in this dissertation can provide an answer to the question: "How can we use the exotic non-linear characteristics of nano devices to build computing systems". This is because, in this study, resonance characteristics of these quantum devices were emulated by using a simple NMOS circuitry and utilized to build a large scale system.

Firstly, a single-core associative processor has been developed featuring resonance (or bell-shaped) characteristics and device characteristics variability problem. The key feature in this work is the proposal of a calibration scheme that can mitigate the problem of device mismatches caused by process variations. In addition, the matching cell requires only eight NMOS transistors to implement, enabling a very compact implementation of a matching-cell array. Furthermore, the matching cell can operate in the subthreshold regime which yields an opportunity of very low-power operation. The prototype chip was fabricated using 0.35-μm CMOS technology. The chip operation has been verified by measurement results.

In order to make the system more intelligent by increasing the number of template data, a multi-core/multi-chip scalable architecture has been developed. The system has the possibility of a large database capacity. The global winner is determined by employing a three-stage time-domain winner-take-all (WTA) circuit. Device mismatch problems as well as decision errors associated with inter-chip communication delays have been resolved by introducing a majority-code-decision circuit. Design ideas have been verified by measurement results of the proof-of-concept chip fabricated in a 0.18-μm CMOS technology.

Nonlinear filters, such as MIN, MAX or MEDIAN filters play an important role in image and speech processing. These filters can be implemented by using rank-order filters (ROFs) by setting appropriate rank-order values. In this regard, an analog implementation of rank-order searching circuit for building ROFs has been developed by using a time-domain computation scheme. The architecture can preserve the accuracy of digital implementations but achieves advantages of analog implementations in terms of low-power dissipation and small chip real estate. The searching function is an important operation in associative processing. Thus, such kind of searching circuit mentioned here is applicable to build not only ROFs but also associative processors. The circuit operation has been verified by experimental results obtained from the prototype chip fabricated in a 0.18-μm CMOS technology.

In some applications where we want to search for not only the nearest-match but also an r-th nearest-match between the input data and template data, we need functions like in rank-order filters. For this purpose, we have developed an r-th nearest-match Hamming distance associative processor inheriting techniques mentioned above. Rank-order searching function is an interesting feature of the proposed architecture, making it different from conventional approaches. The simple configuration achieved in this design comes from the use of only one analog comparator in the rank-order setting circuit for any extension of the number of template words. It enables to combine several rank-order searching circuits in parallel so that a "top-k" of nearest matches can be searched for in parallel. Operation of the system is verified by simulation results of the prototype chip designed in a 0.18-μm CMOS technology.

In this study, we address analog circuit technologies and architectures for building associative processors employed in recognition systems, and illustrate those with examples of prototype VLSI chips: a single-core associative processor employing bell-shaped matching cells, a multi-core/multi-chip scalable architecture for large database capacity, a rank-order searching circuit and a Hamming distance associative processor employing time-domain computation techniques. The advantages of low-power operation and high-density integration inherited from analog circuit technologies were demonstrated, which are attractive features to enhance the performance of recognition systems.

本論文は,Analog Circuit Technologies for Associative-Processor-Based Recognition Systems(和訳:連想プロセッサに基づく認識システムのためのアナログ回路技術 )と題し,人間のように柔軟な認識処理実現を目指し,その基本となる連想プロセッサを低消費電力で且つコンパクトに構築するためのアナログ回路技術に関する研究の成果を纏めたもので,全文6章よりなり,英文で書かれている。

第1章は,序論であり,本研究の背景について議論するとともに,本論文の構成について述べている。

第2章は,Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processorsと題し,所定の入力電圧に対 し出力電流がピーク値をとる共鳴型電流電圧特性を有する素子を用いて連想プロセッサを構成する方法について述べている。直列・並列に4個のNMOSを接続し,各々相補的なゲート電圧で駆動することによりコンパクトな回路構成で共鳴特性を実現している。入力端子に容量を挿入することでテンプレートデータをアナログ値として保持し,入力データとの類似度を電流値として出力するが,微細素子の特性バラツキによるマッチング演算の誤差を低減する新たな回路方式を導入している。このような共鳴回路をマトリクス状に配置することによりアナログ連想プロセッサチップを設計・試作し,実測によりその有効性を実証した。この回路開発は,単電子トランジスタや共鳴トンネルトランジスタ等の量子効果デバイスを用いたシステム構成の方法論を示すという意義も合わせもつ成果である。

第3章は,A Multi-Core/Multi-Chip Scalable Architecture of Associative Processorsと題し,前章で開発した連想プロセッサにおいて,過去の記憶を保持するためのメモリー容量を処理速度を犠牲にすることなく増大させる方式について述べている。所定のメモリー容量を持つマッチング・モジュールを複数個チップ内に設けるとともに,同様のチップを複数個並列に配置することで全体の処理能力を必要に応じて増大できる方式である。パルス信号を用いた時間領域演算のWinner-Take-All(勝者検出)回路を用いているため,チップ間配線のパルス遅延により勝者検出に誤差を生じる可能性があるが,これを防止するための新たな多数決方式を提案している。これらの概念を実証するため,前章よりさらに低電力化した回路方式によるアナログVLSIチップの設計・試作を行い,これによりその有効性を示した。これは重要な成果である。

第4章は,A Rank-Order Searching Circuit Employing Time-Domain Techniquesと題し,最も一致度の高い記憶を探し出すWTAの機能をさらに発展させ,一致度の大きさがr番目である記憶を探し出すための新たなRank-Order探索回路の提案を行っている。電圧振幅0,1のデジタル信号パルスを用いるが,パルス幅によって一致度の大きさを表現する時間領域演算方式に基づき,所定のランクrの記憶の位置でのみ極めて幅の狭いパルスを発生させることによりその位置を同定する方式で,実際にアナログVLSIチップを設計・試作し,実測によりその方式の有効性を実証した。

第5章は,A Hamming Distance Associative Processor Employing Time-Domain Techniquesと題し,0,1のバイナリー値を要素とするベクトルに対し,類 似度のランクオーダ検索を行う連想プロセッサについて述べている。バイナリビットの一致・不一致をパルス信号の遅延量に変換し,前章で開発したランクオーダ検索回路を用いて時間領域演算で実現している。アナログVLSIチップを設計し,SPICEシミュレーションにより有効に動作することを実証した。

第6章は結論である。

以上要するに本論文は,人間のように柔軟な認識処理実現を目指し,その最も基本となる相関演算を共鳴特性を持つ素子を利用して低消費電力且つコンパクトに構築するためのアナログ回路技術を開発するとともに,実際にCMOS回路を用いてVLSIチップを設計・試作・評価し,その有効性を実測結果によって示したものであり,情報学の基盤に寄与するところが少なくない。

よって本論文は博士(科学)の学位請求論文として合格と認められる。