This dissertation focused on the on-chip resonant supply noise reduction methods to improve signal integrity and reliability in multiple power domain LSIs. Power supply integrity is one of the serious problems in the nanoscale LSIs design. The resonant supply noise generated by the rush current is reported that it has typically 40-200~MHz frequency which is determined by the package inductance and the on-chip capacitance. Long duration and large magnitude of the resonant supply noise, especially the first droop, degrades the circuit performance or causes reliability issues. To make sure the circuit performance and improve signal integrity, power supply noise should be reduced and mitigated. Recently, SoCs have multiple power-domain partitions has been developed and commonly used in low-power LSIs such as SoCs. Because all blocks on a chip rarely work simultaneously, there are some blocks in sleep mode. Each sleep block has a lot of parasitic capacitors such as gate capacitance and junction capacitance. These parasitic capacitors in sleep blocks can be used for reducing the resonant supply noise as an alternative to a large decoupling capacitor.

Chapter 2 presents an on-chip resonant supply noise canceller utilizing active parasitic capacitance of sleep blocks. Recent SoCs have multiple power-domain partitions. Because all blocks on a chip rarely work simultaneously, there are some blocks in sleep mode by turning off the foot transistor. Each sleep block has a lot of parasitic capacitors such as gate capacitance and junction capacitance. These parasitic capacitors in sleep blocks can be used for reducing the resonant supply noise as an alternative to a large decoupling capacitor. The test chip was fabricated in a 0.18um CMOS process and measurement results show 43.3% and 39.8% noise reduction, respectively, when the supply voltage is abruptly changed from 1.8V to 1.4V and vice versa. Also, it achieves 12.5% noise cancelling when a sleeping block is turned on the abrupt wake-up of a sleep block. The proposed method requires 1.5% area overhead for four 100k-gate blocks, which is 7.1X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time.

Chapter 3 presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. This work utilizes MOSCAPs instead of the parasitic capacitance of sleep blocks for the effective capacitance value boosting. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The proposed method is possible to improve effective capacitance value of the conventional decaps for reducing on-chip supply noise without discharging time even if SoCs do not have multiple power domains. The measurement results of a test chip fabricated in a 0.18um CMOS technology show 12X boost of the effective decap value, and 65.8% supply noise reduction with 96% settling time improvement. Although the proposed method is required more area than previous work, the capacitor boosting effect gets better because of the small well-substrate junction capacitance.

Chapter 4 presents that switched parasitic capacitors of sleep blocks with tri-mode power gating structure to reduce on-chip resonant supply noise. The test chip is implemented in 0.18um CMOS. Body controls of the sleep blocks make it possible to store charge into the parasitic capacitors of sleep blocks due to reduce discharging time for using charge in the parasitic capacitors of sleep blocks. The proposed method achieves 59.6% and 42.7% noise reduction for wake-up noise and 41MHz periodic supply noise, respectively, without discharging time before noise cancelling, and shows a 8.2x boost of effective capacitance value. The area overhead is 2.2% for 500k-gate logic blocks.

Chapter 5 presents that the controlled bridge impedance to reduce the high frequency noise generated by SPC operations. The proposed method can adjust the amount of injected charge into power supply line by controlling the size of bridges. A test chip fabricated in 65nm CMOS achieves 46.9% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4x boost of effective capacitance value with 2.1% chip area overhead. To apply the proposed switched parasitic capacitors of sleep blocks for reducing resonant supply noise, we can save chip area for noise reduction more effectively.

Now we are sure that these results in this dissertation successfully cancel the on-chip resonant power supply noise generated by the large rush current. It is expected that our research results will make a large contribution to makes more efficient use of the chip area, and improve voltage settling time. As a result, our results will contribute to improve the signal integrity and reliability issues.

本論文は,A Study on Resonant Supply Noise Reduction in Multiple Power Domain LSIs(和訳:多電源ドメイン集積回路における電源共振雑音低減に関する研究)と題し、多電源ドメインを有するシステムLSIにおける,ブロック毎の電源の入り切りや電源電圧の変化により生じる電源共振雑音の低減に関する研究成果を纏めたもので,全6章よりなり,英文で記述されている.

第1章は,序論であり,本研究の背景として,電源の共振雑音,既存の電源雑音低減手法に関して議論するとともに,本論文の構成について述べている.

第2章は,"Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks(スリープブロックの寄生容量を用いた電源の共振雑音低減)"と題し,多電源ドメインにより構成されたシステムLSIにおけるスリープブロックにおいて,電源線から見える寄生容量を,電源の共振雑音に合わせてキャンセル用トランジスタを制御することで,デカップリング容量を用いる手法と比較して小面積で電源雑音を軽減させる手法を提案し,実測による雑音低減の実証とともに解析的に雑音低減効果を示している.

第3章は,"Active Decoupling Capacitor for Cancelling On-Chip Resonant Supply Noise(能動的デカップリング容量を用いた電源の共振雑音低減)"と題し,第2章のスリープブロックの寄生容量における事前の充電時間の軽減を目指し,一般的に雑音低減に用いられるMOS容量を,第2章同様に制御することで,容量当たりの電源雑音低減効果を12倍に向上可能であることを実測により示している.

第4章は,"Switched Parasitic Capacitors of Sleep Blocks with Tri-Mode Power Gating Structure(スリープブロックにおける寄生容量の切り替えに向けた3状態パワーゲーティング構造)"と題し,スリープブロックにおける寄生容量間を,パワーゲーティング用トランジスタに加えブリッジトランジスタを用いることで直列接続―並列接続を切り替えることで,電源電圧変化に起因する共振雑音だけでなく,周期的な電源雑音に対する電源雑音の低減が可能であることを実測により示している.また,スリープブロックを利用することによるリーク電流増大の影響をシミュレーションにより検証している.

第5章は,"Controlled Bridge Impedance for Switched Parasitic Capacitors(寄生容量切り替え構成におけるブリッジインピーダンスの制御)"と題し,第4章で提案したスリープブロックにおける寄生容量の切り替えにおいて生じる高周波雑音の低減のために,ブリッジトランジスタの駆動力調整機能を設けることで,電源雑音低減効果の調整が可能となることを実測により示している.

第6章は,結論である.

以上要するに本論文は,多電源ドメインを有するシステムLSIにおいて,電源に生じる共振雑音を低減する手法の提案を行い実測により実証したもので,半導体電子工学の発展に寄与するところが少なくない.

よって本論文は博士(工学)の学位請求論文として合格と認められる.