This thesis focuses on CMOS circuit building blocks for proximity communication systems which are intended for connecting generic low power modules together to form diverse systems which are both low power and have small form factors to fill the cost and performance gap between systems made on boards and custom LSIs.

This thesis is made up of six chapters. The first chapter gives the motivations and goals of this thesis. Proximity communication using inductive coupling and capacitive coupling is a promising way to connect generic low power modules together to form diverse systems. Reconfigurability, high mechanical reliability, low power dissipation, and low implementation cost are some of the significances of proximity communication. A comparison of inductive coupling communication and capacitive coupling communication is given as well as a review of conventional circuits. An overview of this thesis is presented in the final part of this chapter.

Board to board communication using proximity communication can be used instead of conventional mechanical connectors, for high reliability connections in places where vibration or dust can accumulate, while keeping a small footprint. In chapter 2, three types of transceivers for board to board communication are proposed. The first circuit is a capacitive coupling channel with a track and charge scheme. This scheme enables fast reset while eliminating DC leakage paths, allowing the capacitive pads to be exposed, instead of covered with solder mask, enabling the communication distance to be closer and thus reducing the pad size. The second circuit copes with the DC leakage between the transmitter and receiver circuits using capacitors inserted in series with the coupling capacitors. This simple architecture can be used to send clock signals as well as high speed data. Finally, an inductive channel for longer communication distances is explored. One main drawback of inductive channels is the density of inductors that can be placed due to inter-channel crosstalk. This is coped by introducing rectangular inductors. The effect of the inductor shape on the crosstalk is discussed.

Chip to chip stacking in a package is also a place where proximity communication shows much promise. Conventional proximity channels have shown the potential to connect multiple chips, but LSIs using proximity channels must be separately designed and manufactured since the I/O cannot be shared with conventional bond wire implementation. To overcome this problem, a novel implementation of chip to chip communication using Through Silicon Capacitive Coupling (TSCC) is proposed in chapter 3. TSCC has three features, (1) it allows stacking more than three chips, (2) it enables easy access to the bonding pads for DC power supplies, and (3) it enables the capacitive coupling pads to be used as bonding pads. This allows the I/O to be used for both TSCC and traditional wire bonding, eliminating the need to redesign the chip for both cases. Measurements of chips implemented with TSCC are presented to show the feasibility of this interface.

In low power modules using proximity communication, one of the most power hungry circuit blocks is the clock distribution. In chapter 4, a Switched Resonant Clocking (SRC) scheme is proposed to reduce the power dissipated in the clock distribution. In conventional resonant circuits, when the clock frequency is lower than the designed frequency of the resonant tank, series resonation between the inductor and capacitor inserted to cut DC current occurs and causes large power dissipation and double switching. This makes low speed testing difficult in conventional circuits. This problem is addressed by adding a switch between the inductor and DC cut capacitor, which is turned off at low clock frequencies to prevent series resonance, while reducing the power dissipation in the clock distribution at higher frequencies.

Other circuit blocks to lower the power consumption of proximity communication systems are described in chapter 5. First, post fabrication tuning of logic circuits using gate oxide stress is proposed. This applies high voltage stress selectively on certain gates to relax the inherit mismatch between logic thresholds between gates in logic circuits, thereby lowering the minimum operational voltage of the circuit (VDDMIN). Feasibility of implementing this topology into several different types of logic circuits is explored. Next, a low power voltage reference circuit is proposed. This uses the threshold voltage difference of different types of transistors to make the output voltage. This circuit has a higher output voltage compared to conventional voltage reference using similar topologies. Threshold voltage tuning is also applied here to control the output voltage.

Chapter 6 concludes this thesis.

本論文は「CMOS Circuit Building Blocks for Proximity Communication Systems」(和訳:非接触通信システムに向けたCMOS要素回路の研究)と題し、非接触通信を将来のシステム実装方法として使用する際に必要となる各種回路ブロックに関し、送受信フロントエンド回路を含む要素回路をCMOS集積回路で実現する手法を提示するもので、全7章で構成されている。

第1章は「Introduction」(序論)であり、非接触通信を用いたシステムの要求事項や課題について述べるとともに、本研究の背景を述べ、目的を明確化している。

第2章は「10μm Range Board to Board Proximity Communication」(通信距離10μmのボード間非接触通信)であり、通信電極の面積が従来比1/25の50μm角の電極で通信を可能とする2つの回路手法を提案している。一つはデータ通信に向くトラック・アンド・チャージ手法で、低ビットレート15Mbpsで従来比1/20以下の低消費電力を実現する。1Gbpsまでの通信を65nm CMOSチップで実証した。他の一つはクロック伝送に向く方式で、受信フロントエンドに直列容量を挿入することを提案し、2.6Gbpsという高速通信を65nm CMOSチップで実証している。

第3章は「200μm Range Board to Board Proximity Communication」(通信距離200μmのボード間非接触通信)であり、通信距離が200μmほどある応用を想定し、誘導結合通信を用い、隣接コイル間の干渉を下げつつ、信号量を増大させるコイルの最適設計指針とリンギング抑制手法を提示している。0.18μm CMOS技術による実測でその有効性を示している。

第4章は「Chip to Chip Proximity Communication」(チップ間非接触通信)であり、非接触通信用電極と通常の実装で用いるボンディングパッドを共用することによって、同一デザインで2種類の実装を可能とする容量結合型スルー・チップ通信を提案し、400μm厚のチップを介して、200Mbpsで信号を授受できることを0.18μm CMOSチップで実証している。

第5章は「Clocking」(クロッキング)であり、クロック周波数を動的に変化させる非接触通信システムで、スイッチ付き共振クロック回路を用いて、クロック系の消費電力を最大93%削減すると共に、誤作動を防止できることを0.18μm CMOS技術による実測で示している。

第6章は「Low Voltage Reference Voltage Circuit」(低電圧基準電圧回路)であり、ストレス印加によって基準出力電圧調整を行える出力電圧0.6Vの基準電圧発生回路を提案し、40nm CMOS技術を使って試作し評価している。また、実測結果を踏まえ、シミュレーションを通して改良手法を提示している。

第7章は「Conclusions」(結論)であり、本研究の成果を要約している。

以上のように本論文は、非接触通信技術をワイヤレスコネクタなど新たな実装方式として使用する際に必要となる低電力CMOS要素回路技術として、トラック・アンド・チャージ手法、リンギング抑制手法、容量結合型スルー・チップ通信、スイッチ付き共振クロック回路を提案し、その有効性を集積回路の設計・試作・測定を通じて実証したものであって、電子工学上寄与するところが少なくない。

よって本論文は博士(工学)の学位請求論文として合格と認められる。