This thesis explores possibility for realization of sub-0.5V extremely low power logic circuits. Transistor variations at low power supply voltage degrade the operation of logic circuits. Thus, the effects of transistor variations are investigated at low VDD and countermeasures against them are proposed in the thesis.

Reduction of power supply voltage (VDD) is an effective method for achieving ultra low power logic circuits since active power is proportional to VDD2 and leakage power is proportional to VDD. Although circuits exhibit slower speeds at low supply voltage, the trade-off between power and operation frequency remain attractive for energy-constrained systems. Besides, when VDD is near/below the threshold voltage of transistors, logic circuits operate most efficiently. In this way, lowering power supply voltage achieves low power and energy efficient operation. Transistor variations, however, inhibit lowering VDD because the sensitivity of circuits to transistor variations drastically increases under reduced VDD. The main obstacles for low voltage operation of logic circuits are function errors and delay variations of logic circuits, because one function error at a single logic gate is considered as the function error of whole circuits and the delay variations makes the design of logic circuits more difficult at low VDD. These problems must be dealt with properly in design of low voltage logic circuits. Thus, the purpose of the thesis is to reveal the effect of these two problems on logic circuits and propose countermeasures to achieve sub-0.5V extremely low power logic circuits.

At first, function error of logic gates is discussed in 65nm CMOS. Function errors prevent lowering V(DD) of logic circuits. The minimum operating voltage (V(DDmin)) is defined as the minimum power supply voltage when the circuits operate without function errors. V(DDmin) increases with the number of logic gates and CMOS technology down-scaling. Thus, reducing V(DDmin) of logic circuits is important to achieve extremely low voltage logic circuits. The determinant factors of V(DDmin) in logic circuits are investigated, and the design criteria to reduce V(DDmin) are presented. V(DDmin) consists of V(DDmin)(SYS) and V(DDmin)(RAND). V(DDmin)(RAND) which is random component of V(DDmin) depends on the random variation of threshold voltage of transistors and the number of stages of logic gates, while V(DDmin)(SYS) which is systematic component of V(DDmin) is determined by the balance of nMOS and pMOS and is minimized when the logic threshold voltage is equal to half VDD. Therefore, V(DDmin)(RAND) is reduced by increasing width of nMOS and width of pMOS, while V(DDmin)(SYS) is minimized by optimizing WP/WN at a design stage. The body-biasing is effective to compensate for the increase of V(DDmin)(SYS) due to the die-to-die VTH variation. The optimal body-biasing minimizes V(DDmin)(SYS) and the forward body biasing decreases V(DDmin)(RAND). In the measurement, V(DDmin) is successfully reduced by 45mV from 193mV to 148mV by the forward body biasing.

Next, the effect of delay variations on logic circuits is explored in 65nm CMOS. Delay variations of logic gates make it difficult for logic gate paths to meet timing constraints. If enough setup time margins are considered, operation frequency decreases. By contrast, to meet hold time constraint, hold compensation buffer is inserted into logic gate paths. Therefore, the within-die delay variation dependence on VDD in several types of design under tests (DUT's) is measured with a proposed circuit. The proposed circuit emulates a real logic path because device under tests (DUT's) are inserted between F/F's and F/F-related delays are included in the delay measurement. The main focus of the measurement is dependence of the logic circuits on the methodology of physical layout. Although, Layout of logic circuits is usually designed by automatically using place and route (P&R) tools, the effect of the auto P&R layout on delay variation is not clear at low voltage. Thus, DUT delay dependence on methodology of physical layout is investigated. The measurement result reveals that relative delay variation difference (=sigma/average) between the manual layout and the P&R layout rapidly decreases from 1.56% to 0.07% with reducing VDD from 1.2V to 0.4V, because the random delay variations due to the random transistor variations dominate total delay variations at low VDD. This result indicates that low voltage logic circuits designed by P&R tools do not raise delay variations at low VDD.

Finally, in order to achieve ultra low VDD logic circuits, a post-fabrication dual supply voltage (VDD) control (PDVC) of multiple voltage domains is proposed. Reducing V(DDmin) at a design phase is difficult because V(DDmin) is mainly determined by random variations of transistors. Furthermore, only one functional error of logic gates increases V(DDmin) of a whole logic circuit. Therefore, in order to reduce V(DDmin), VDD must be controlled with multiple domains. In the proposed PDVC, the layout of the whole logic circuit is divided into many domains regardless of the functional blocks. The VDD of each domain is independently selected from high VDD (VDDH) and low VDD (VDDL). PDVC is applied to a DES CODEC's circuit fabricated in 65nm CMOS. The layout of DES CODEC's is generated by P&R tools and divided into 64 VDD domains. VDDH or VDDL is applied to each domain and the selection of VDD's is performed based on multiple built-in self tests. VDDH is selected in V(DDmin)-critical domains, while VDDL is selected in V(DDmin)-non-critical domains. As a result, a maximum 24% power reduction was measured with the proposed PDVC at 300kHz, VDDH =437mV, and VDDL=397mV.

The results of the thesis, which includes investigation on and countermeasures against V(DDmin) and delay variation, is useful to realize sub-0.5V extremely low power logic circuits for future LSI applications.

本論文は「Sub-0.5V Extremely Low Power Logic Circuits」(和訳:電源電圧0.5V以下の極低電力ロジック回路に関する研究)と題し、ロジック回路の低電源圧化を妨げる問題を分析し、その対策を示すことで、電源電圧0.5V以下のロジック回路を実現するための手法を提示するものであり、全5章で構成されている。

第1章は「Introduction」(序論)であり、低電源電圧ロジック回路を実現する意義と、低電源電圧化を妨げる問題を示すとともに、本研究の背景を述べ、目的を明確化している。

第2章は「Analysis and reduction of minimum operating voltage of logic circuits」(ロジック回路の最低可動電圧の解析と低減)と題し、論理ゲートが正常に動作する下限電圧である最低可動電圧の決定要因を、65nm CMOSにおいて実測、理論、シミュレーションを元に分析し、その低減を可能にする設計手法について論じている。最低可動電圧はnMOSとpMOSのバランスによって決定されるシステマチック成分と、トランジスタのランダムしきい値ばらつきによって決定されるランダムばらつき成分に分解できることを明らかにした上で、両成分を低減する設計手法を論じ、ロジック回路の低電源電圧下を実現するための論理ゲート、Flip Flopの設計手法を確立した。

第3章は「Analysis of delay variation」(遅延時間ばらつきの解析)と題し、論理ゲートの遅延時間ばらつきを測定する回路を65nm CMOSで試作、測定し、論理ゲートの遅延ばらつきを分析している。特に自動配置配線ツールによるレイアウト、手動レイアウトの二つのレイアウト手法が相対遅延時間ばらつきに及ぼす影響について分析し、電源電圧を1.2Vから0.4Vに低減すると両者の相対遅延時間ばらつきの差が1.56%から0.07%に減少することを示し、低電源電圧ロジック回路設計においても、レイアウト手法は従来の設計手法が適用可能であることを実証した。

第4章は「Post fabrication dual power supply voltage control」(電源電圧の製造後制御)と題し、電源電圧の製造後制御によりロジック回路の実効的な最低可動電圧を低減し低電力化を実現する手法を提案し、65nm CMOSでの試作を通じてその有効性を実証している。提案手法は、ロジック回路を機能ブロックとは無関係に機械的に細かく分割し、各領域に与える電源電圧を提案する最適化アルゴリズムにより決定することで、ロジック回路全体の実効的な最低可動電圧を低減し電力を削減するものであり、最大で24%の電力削減を実証した。

第5章は「Conclusion」(結論)であり、本研究の成果を要約し結論を述べている。

以上のように本論文は、電源電圧0.5V以下の極低電力ロジック回路の実現を目的として、ロジック回路の低電源電圧化を妨げる最大の要因である最低可動電圧の決定要因を分析し、低電源電圧向け論理ゲートとFlip Flopの設計手法を確立するとともに、電源電圧の製造後制御によりロジック回路の実効的な最低可動電圧を低減し低電力化を実現する手法について集積回路の設計・試作を通じて実証したものであって、電子工学上寄与するところが少なくない。

よって本論文は博士(工学)の学位請求論文として合格と認められる。