Recently it is becoming increasing difficult to further improve the performance of Si MOSFETs, because the conventional device scaling is approaching its physical limit. Therefore, the Ge is considered as one the most promising channel materials serving in future CMOS devices due to its high bulk electron and hole mobility. For revealing high performance Ge CMOS devices, advanced high-k/Ge gate stacks with both thin EOT and low D(it) are mandatory. In this research, we focus on the fabrication technique for the Ge gate stacks with thin EOT and high quality MOS interfaces simultaneously. The Ge CMOS devices with these thin EOT and low D(it) gate stacks are also demonstrated.

First, the drawback of the conventional fabrication technique, which is depositing high-k after the IL formation, is examined by applying an ALD Al2O3 on GeO2/Ge structures. It is found that the GeO2/Ge MOS interface degrades significantly with decreasing the GeO2 IL thickness to 1.5 nm, due to the damages induced by high-k deposition. We found that although the GeON/Ge MOS interfaces formed by an in-situ plasma nitridation of GeO2/Ge structures exhibit stability, the EOT scaling is still limited by the difficulty in growing ultrathin GeO2 layers and the degraded GeON/Ge MOS interface attributed to N cooperation. By optimizing the GeON thickness and N content, an thinnest EOT of 2.2 nm and a relatively low D(it) of 4~5×10(11) cm(-2)eV(-1) have been revealed using an Al2O3 (2 nm)/GeON (1.5 nm)/Ge gate stack with a N/Ge ratio of 0.34 in the GeON IL, indicating the intrinsic EOT scaling limit with maintaining a superior MOS interface using a conventional process.

In order to overcome the limit of conventional fabrication process, a plasma post oxidation methodology has been purposed to form a GeOx IL beneath an Al2O3 capping layer by exposing oxygen assisted electron cyclotron resonance (ECR) plasma to a thin ALD Al2O3/Ge structure. Here the GeOx IL is free of the high-k formation induced damages. In addition, the Al2O3 capping layer serves as a protection to the thin GeOx IL against the harmful species in the atmosphere. The low temperature during the plasma post oxidation can also prevent the thermal damage to thin GeOx/Ge interfaces. The structure and chemical components of these Al2O3/GeOx/Ge structures are analyzed in detail. It has been confirmed that by adjusting the Al2O3 capping layer thickness and plasma condition, the thickness of GeOx IL can be precisely controlled down to 0.3 nm. The growth behavior of the GeOx ILs has been investigated using both Ge (100) and (111) substrates. It is observed by both X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) that the GeOx/Ge interface formed by a 300 oC plasma post oxidation exhibits relatively large interface roughness. In contrast, the GeOx IL evolutes layer-by-layer atomically with a room temperature plasma post oxidation, yielding a atomic flat GeOx/Ge interface.

The electrical properties of the Al2O3/GeOx/Ge gate stacks formed by plasma post oxidation have been investigated systematically. Through the comparison of the MOS interface qualities of Al/Al2O3/GeOx/Ge MOS capacitors fabricated by a conventional procedure and the plasma post oxidation method, it is confirmed that the plasma post oxidation shows significant advantage in revealing a lower D(it) under a thinner EOT. The properties of GeOx/Ge MOS interfaces fabricated with various conditions are characterized. It is found that the plasma power, the post oxidation time and the Al2O3 thickness do not affect the GeOx/Ge MOS interface quality. The GeOx IL thickness is the dominating factor of the D(it) and it is confirmed that a GeOx IL as thin as 0.5 nm is sufficient to suppress the D(it) at the GeOx/Ge interface. This thickness of GeOx corresponds to the EOT of 0.35 nm, indicating the feasibility of further EOT scaling of low D(it) Ge gate stacks using the plasma post oxidation methodology. From the view point of chemical components of GeOx ILs with different thicknesses, it is interestingly found that the complete oxidation state (GeO2) is not necessarily needed to guarantee a low D(it), which is a complement to previous theory. With an optimization of the Al2O3/GeOx/Ge gate stack structure and the plasma conditions, a sub-nm EOT of 0.98 nm has been realized with a low D(it) in the 10(11) cm(-2)eV(-1) order.

The Ge p- and n-MOSFETs have been realized using the Al2O3/GeOx/Ge gate stacks formed by plasma post oxidation. The record high hole of 401 cm2/Vs and electron mobility of 693 cm2/Vs are achieved at a sub-EOT of 0.98 nm for the (100) Ge p- and n-MOSFETs, respectively. The impact of the EOT scaling has been investigated for these Ge p- and n-MOSFETs and it is found that the hole and electron mobility of Ge p- and nMOSFETs can still be improved by reducing the column scattering center at the MOS interface even at an EOT region of ~1 nm. Also, it is confirmed that the rapidly increase of slow traps near the conduction band edge of Ge causes stronger degradation of Ge nMOSFETs with scaled EOT. Therefore, sufficient passivation of these slow traps would be another booster to further improve the performance of Ge nMOSFETs. By revealing an atomic flat GeOx/Ge interface through a room temperature plasma post oxidation, it is also found that the high field mobility of the Ge p- and n-MOSFETs improve around 20% and 25% at Ns=10(13) cm(-2), compared with the Ge p- and n-MOSFETs with a normal GeOx/Ge interface fabricated by 300 oC plasma post oxidation. By comparing with the results in previous reports, it is confirmed that the mobility degradation with EOT scaling can be sufficiently suppressed with the superior MOS interface passivation by present Al2O3/GeOx/Ge gate stacks. For the (100) Ge pMOSFETs, an improvement of 80% has been revealed compared with previous reports with a comparable EOT of 0.98 nm. For (100) Ge nMOSFETs, current Ge nMOSFETs exhibits a 3.1 times higher peak mobility than that reported in previous researches under an EOT of 1.2 nm.

In order to further scale down the EOT of Ge gate stacks beyond 1 nm, the plasma post oxidation method is also extended to HfO2 based Ge gate stacks. However, during the plasma post oxidation of HfO2/Ge structures, a uniform HfxGeyOz layer with a poor HfxGeyOz/Ge interface is formed rather than an HfO2/GeOx structure due to the strong atom pumping property of HfO2. In this research, an Al2O3 diffusion control layer (DCL) is introduced between the HfO2 and Ge to suppress the inter-mixing between HfO2 and GeOx during the plasma post oxidation. It is found that 0.2 nm is the minimum thickness for the Al2O3 DCL to sufficiently prevent the HfO2-GeOx inter-mixing and form a high quality GeOx/Ge MOS interface. By changing the plasma post oxidation time, it is confirmed that the formation GeOx IL is the key to reveal a low D(it) in this HfO2 based gate stack. Especially, with the help of 0.2-nm-thick Al2O3 DCL, an EOT of 0.76 nm and a D(it) of 2×10(11) cm(-2)eV(-1) have been realized for the HfO2 (2.2 nm)/Al2O3/Ge structures after a room temperature plasma post oxidation, where a 0.35-nm-thick GeOx IL is formed.

The (100) Ge p- and n-MOSFETs have also been fabricated using the HfO2/Al2O3/GeOx/Ge gate stacks having 2.2-nm-thick HfO2, 0.2-nm-thick Al2O3 and different plasma post oxidation time. By combining the low D(it) GeOx/Ge MOS interfaces formed using an Al2O3 DCL and an atomic flatness for the GeOx/Ge interface revealed by room temperature plasma post oxidation, both high peak mobility and high field mobility is realized for the HfO2/Al2O3/GeOx/Ge p- and n-MOSFETs which is comparable or even higher than those in Ge MOSFETs with thick (~20 nm) GeO2/Ge gate stacks, under an EOT of 0.7~0.8 nm. Especially, record high hole mobility of 596 and 546cm(-2)/Vs have been realized under EOT of 0.82 and 0.76 nm for the HfO2/Al2O3/GeOx/Ge pMOSFETs. For the Ge nMOSFETs, the peak electron mobility of 690 and 754cm(-2)/Vs are achieved using the HfO2/Al2O3/GeOx/Ge gate stacks having EOT of 0.76 and 0.82 nm. Compared with the reported data, a 5.1 times improvement of peak hole mobility is realized for the (100) Ge pMOSFETs with present HfO2/Al2O3/GeOx/Ge gate stack under a similar EOT of 0.8 nm. For the Ge nMOSFETs, this research demonstrates the thinnest EOT ever reported in the world.

This research systematically investigated the properties of thin EOT Ge gate stacks. A plasma post oxidation methodology has been purposed to fabricate the GeOx IL in thin EOT and high quality Ge gate stacks. The properties of thin GeOx/Ge interface have been investigated in detail. The high mobility Ge CMOS devices are also demonstrated using the plasma post oxidation Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks with sub-EOT. This research indicates the feasibility of the plasma post oxidation technique in future scaled CMOS technology.

本論文は、Formation of Ge Gate Stack Structures by Plasma Post Oxidation and Their Applications to Ge CMOS Devices (和訳:プラズマ後酸化によるGeゲートスタック構造の形成とGe CMOS素子への応用)と題し、将来の高性能MOSFETのチャネルとして期待されているGeのMOS界面特性向上のための界面制御技術とMOS界面特性、及びこの界面をCMOSに適用することで実現されたMOSFETの電気特性に関する研究成果を纏めたもので、全文9章よりなり、英文で書かれている。

第1章は、序論であり、本研究の背景について議論すると共に本論文の構成について述べている。

第2章は、「Fabrication and Devices Analyzing Techniques in This Research」と題し、本研究において素子作製に用いたALD (Atomic Layer Deposition)法の原理、物理解析に用いたXPS (X-ray Photoelectron Spectroscopy) 法や界面準位、移動度の電気評価手法について述べている。

第3章は、「Suppression of ALD Induced Damage to GeO2/Ge MOS Interfaces by In-Situ Plasma Nitridation」と題し、GeO2界面層上へのALD膜堆積時に発生する界面劣化を抑制する方法として、GeO2表面をプラズマ窒化する方法を提案し、MOS界面特性の向上の結果およびこの方法によるゲート絶縁膜薄膜化の限界について述べている。

第4章は、「Plasma Post Oxidation of Al2O3/Ge Structures」と題し、極薄の等価ゲート絶縁膜厚(Equivalent Oxide Thickness(EOT))のGeゲート絶縁膜を実現する方法として、Ge上に直接堆積したAl2O3の上からECR(Electron Cyclotron Resonance)酸素プラズマによる酸化を行い、Al2O3とGeの間にGe酸化膜を形成する方法を提案し、この方法により形成された界面層の構造を明らかにすると共に、原子層オーダーでのGe界面の酸化が実現できることを実験的に明らかにしている。

第5章は、「Electrical Properties of Al2O3/GeOx/Ge Gate Stacks」と題し、第4章にて提案された方法で作製したMOS界面の界面特性、特に界面準位とGe酸化膜界面層との関係を定量的に調べ、Ge酸化膜界面層膜厚によって、界面準位が統一的に決定されることを明らかにしている。

第6章は、「High Mobility and Thin EOT Ge CMOS Devices with the Al2O3/GeOx/Ge Gate Stacks」と題し、第4章で提案されたGeゲートスタック構造を用いて、Ge n-MOSFETおよびp-MOSFETを作製し、その電気的特性を調べた結果を示している。提案した方法による優れたMOS界面特性を反映して、0.98 nm のEOTをもつ(100)Ge上のn-MOSFETとp-MOSFETにおいて、それぞれ、693 cm2/Vsと401 cm2/Vsという高いピーク値の電子および正孔移動度が実現できることを示している。

第7章は、「Mobility Degradation Mechanism and Mobility Improvement in Ge MOSFETs in High Ns Region」と題し、Al2O3/GeOx/Ge MOSFETの移動度の決定機構、特に高誘起キャリア濃度領域での移動度低下の機構を明らかにするため、ホール測定及び移動度の温度依存性の評価を行い、バンド内界面準位の影響と表面ラフネス散乱の影響があることを明らかにすると共に、低温酸化を用いた界面凹凸の低減によって、移動度が向上することを示している。

第8章は、「Aggressive EOT Scaling by Plasma Post Oxidation of HfO2-based Gate Stacks」と題し、EOTの更なる低減のため、HfO2/Al2O3/Geをプラズマ後酸化することにより、0.8 nm 前後のEOTのHfO2/ Al2O3/GeOx/Ge構造が実現できることを示し、この方法を用いて0.82 nmのEOTの下で、754 cm2/Vsと596 cm2/Vsという高い移動度のGe n-MOSFETとp-MOSFETが実証できることを示している。

第9章は、結論と今後の展望を述べている。

以上要するに本論文は、将来の高性能MOSFETのチャネル材料として期待されているGeのMOS界面特性向上とEOT低減を両立できる界面制御技術として、Ge上にAl2O3及びHfO2/Al2O3を堆積した後、ECR酸素プラズマを照射することによってGe MOS界面にGe酸化層を形成する方法を提案し、1 nm 以下のEOTにおいても極めて低い界面準位密度を実現し、このゲートスタック構造を用いた高移動度のn-チャネルおよびp-チャネルMOSFETの動作実証を行うと共に、作製された界面の構造とそれがMOSFETの電気特性に及ぼす影響を明らかにしたものであり、電子工学上、寄与するところが少なくない。

よって本論文は博士(工学)の学位請求論文として合格と認められる。